As mentioned in MultiCore: Cell Architecture Explained, this week at the International Solid State Circuits Conference (ISSCC) more details of the Cell will be present by STI (Sony, Toshiba, and IBM).
The Cell chip, computer experts said, could have a theoretical peak performance of 256 billion mathematical operations per second. With that much processing power, the chip would have placed among the top 500 supercomputers on a list maintained by scientists at the University of Mannheim and the University of Tennessee as recently as June 2002….the Cell architecture is distinguished by the fact that it controls an array of eight additional processors that the design team refers to as synergistic processing elements, or S.P.E.’s. Each of the S.P.E.’s is a 128-bit processor in its own right.
So, Supercomputer on a chip?!..
128 bit processor (leaping over 64 bit processors) NYT’s go it wrong, rather “128 x 128-bit registers”…BBC has a similar piece.
JoyStiq worries Will Sony Kill the Cell Chip with Security, based on a ZdNet article and comments that “a number of on-the-chip security measures, mostly aimed at preventing unauthorized copying or distribution of copyright content”. This is very briefly mentioned by Nicholas Blachford under DRM in the Hardware, and maybe a side effect of the Cell grid on a chip Architecture, but sounds a lot like “Trusted Computing”. (See EFF:Trusted Computing: Promise and Risk piece for background).
The Register has an excellent analysis in:The Cell chip – what it is, and why you should care, plus The Cell Chip – how will MS and Intel face the music?
Also in regard to the Nicholas Blachford article : Cell Architecture Explained, Ars Technica criticed it in Cell “analysis” a mixed bag, Nicholas reponded with Updates, Clarifications and Missing Bits and a direct Rebuttal.
See MultiCore for more.
Update: from Electronics Weekly, Wired and some pictures (via episteme.arstechnica we have links to images